The semiconductor or integrated circuit (IC) industry aims to manufacture ICs with higher and higher densities of devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This desire for large scale integration has led to a continued shrinking of circuit dimensions and device features. However, as device features become smaller, required device performance and functionality have increased. For example, capacitors, which are typical devices integrated into integrated circuits, are becoming smaller and smaller. Nevertheless, IC design still requires large charge storage from the capacitors.
Vertical plate capacitors are one type of capacitor used in IC design. The design and fabrication of present-day vertical plate capacitors suffer from several challenges. In some cases, such as when the density of neighboring circuitry is relatively low, the dimensions of a vertical plate capacitor can be increased to increase charge storage of the capacitor. However, in other cases, such as when the density of neighboring circuitry is high, the dimensions of the capacitor may be restricted, thus resulting in a vertical plate capacitor with less than desired capacitance. For example, one typical type of vertical plate capacitor has sets of two electrodes, each electrode having multiple fingers or interconnects coupled to a stub, with the interconnects of each electrode interdigitated with the interconnects of the other. Each set of electrodes is formed in a dielectric material layer with multiple sets of electrodes overlying each other in a stacked formation. Vias are formed in dielectric layers interposed between the sets of electrodes to couple adjacent, stacked electrode sets. Typical vertical plate capacitors may have five to eight layers of electrode sets and hundreds of vias coupling stacked electrode sets. To achieve high capacitance, the interconnects of each electrode are relatively long so that there is large area of overlap between the interconnects of the same dielectric layer. However, because the electrodes typically are formed in a dielectric layer using a damascene process, the interconnects are only as thick as the dielectric layer in which the electrodes are formed. The capacitance generated between overlying electrodes and that generated between vias within the same dielectric layer do not contribute substantially to the overall capacitance of the device. Thus, the overall capacitance of the vertical plate capacitor is limited by the interconnects' thicknesses or heights.
Further, while the average thicknesses of the interconnects limit the overall capacitance of the vertical plate capacitor, variations within the metal density of the interconnects and other metals structures within the same dielectric layer may pose problems in the operation of the capacitor-containing device and, hence, decrease device yield. The longer the interconnects are, the more likely there are to be substantial metal density variations in the layer. Although the overall metal density of the interconnects and other metal features in a dielectric layer of the device is determined by fabrication standards, variations in the metal density of the interconnects and the other metal features may result from the routing design of the various circuits. This mismatch in the metal densities of the capacitance regions and the circuit regions may, in turn, result in metal height variations after chemical mechanical planarization (CMP) is performed. Such metal height variations increase the difficulty of CMP optimization and may result in inferior CMP planarization effects, such as underpolishing, otherwise known as metal puddling, that causes electrical shorting, or overpolishing that causes electrical open circuits. In addition, such inferior CMP planarization may result in on-chip resistance and capacitance variations.
Accordingly, it is desirable to provide a density-conforming vertical plate capacitor that can provide larger capacitance than prior art capacitors without an increase in interconnect length or height. In addition, it is desirable to provide a density-conforming vertical plate capacitor with via bars that contribute substantially to the overall capacitance of a device. It also is desirable to provide a method for fabricating a density-conforming vertical plate capacitor that results in improved metal height uniformity. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.